@ the Biped Lab
Equalizer for 3DIC
Having learned about integrated circuit procedures in my junior year, I began contemplating whether it would be possible to transform the aforementioned into a three-dimensional package instead of the traditional two-dimensional package, as integrated circuits do reach a physical limitation in terms of molecule scale. I decided to do a project on this topic following discussions with Prof. Tzong-Lin Wu, Director of the Graduate Institute of Communication Engineering (GICE) and the Communication Research Center (CRC). I started by looking into ways of compensating for the loss of TSV—a key point in 3D-IC communication—by analyzing the eye diagram and equalizer. For this, we first compared numerous TSV models with the circuit model in Keysight (Agilent) Advanced Design System (ADS) and ANSYS High Frequency Structure Simulator (HFSS) to verify accuracy, and constructed a precise two-TSV digital system in ADS with a bitrate from 5G to 60G, a diameter of TSV from 5mm to 30mm, and a distance between the two TSVs from 150mm to 300mm. Although TSVs have many advantages, such as low power consumption, high-speed signal propagation and processing, and reduced connection lengths and improved channel bandwidth, we found that there was significant high-frequency signal loss, current leakage, and inter-symbol interference (ISI). These issues made the eye diagrams look bad and created a situation in which |S21| decays rapidly. Thus, we constructed mathematical models of RC and RL equalizers to enhance the |S21| and eye diagrams, which we compared with Matlab. After substantiating the mathematic models, we were able to specifically control how much the equalizer will compensate the S21, and further improve the eye diagram. We constructed a standard operating procedure for both the RC and RL equalizers, from which others can easily create the equalizer with certain parameters.